Integrated circuit devices often contain a number of embedded memory arrays, each memory array having a predefined number of memory cells. The amount of utilization of the memory arrays varies depending on the application of the device. In many cases, the memory arrays are only partially utilized. These unused portions of the memory array unnecessarily use power, causing the total power used by the device to be higher than it would be otherwise. Transistor technology scaling aggravates the problem as leakage current increases significantly with the shrinking of the process node.
The size and number of memory arrays of a device are defined based on the expected target applications. For example, one thousand 8 kilobits (kb) (16 bits wide by 512 bits deep) memory arrays are embedded in a typical four million logic gate device. However, due to varied customer applications, the utilization of the memory arrays varies greatly. In an example, a design may need a number of 144 kb memory arrays, each memory array configured as 144 bits wide by 1 kb deep. Each of the 144 kb memory arrays may be configured by cascading nine 8 kb memory arrays (9×16 bits=144 bit wide). In this configuration, the memory utilization for each 8 kb memory array would be 12.5% (1 kb out of the 8 kb).
For applications that have low memory utilization and require low power dissipation, it is disadvantageous for the device to use the full amount of power when memory array resources are not fully used. As a result, there is a need to solve the problems of the prior art to provide a method and apparatus for reducing power used by an integrated circuit by providing power to selective portions of a memory array.